Job Description

Ref No.:18-00133
Location: Portland, Oregon
Senior RTL/Verilog/ASIC Developer
Portland, OR
6-9 month contract with likely extension or conversion to FTE

Are you looking for an exciting opportunity to own complex projects and dramatically change client's lives? We are looking for a motivated, self-starter that has experience working in a small development environment with proven experience with complex RTL/Verilog design and architecture.
If this sounds like you then we want to hear from you!

Job Description:
5+ years of industry experience in the following areas:
  • ASIC front end development.
  • Logic design, RTL coding, verification, synthesis, and timing closure.
  • Hardware description languages (Verilog, System Verilog and/or VHDL).
  • Mentor Questa/Modelsim or similar tools a plus.
  • Synopsys DC/PrimeTime or similar tools a plus.
  • Scripting/programming in C/C++, TCL, Perl/CSH a plus.
  • Verification experience a must
  • UVM a big plus
Experience with One or More:
  • Video and image processing based systems
  • High speed SerDES interfaces
  • Video and image compression
Should Have:
  • Proven ability to work in a small company environment
  • Ability to work independently or as part of a small team

Education: BS/MS - Electrical Engineering

Application Instructions

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